Typically, Integrated Circuits (ICs) are provided with ElectroStatic Discharge (ESD) protection circuitry. The ESD protection circuitry protects parts of an integrated circuit by clamping ESD-stressed terminals during an ESD event, and serves to divert an electrostatic discharge current away from protected parts of the integrated circuit, and thus to dissipate the “stress” energy without damage to the integrated circuit.
It is known for integrated circuits provided with power gating capabilities to comprise such ESD protection circuitry. Such integrated circuits typically include one or more so-called “gating switches” on-die, the gating switches being a kind of semiconductor switch that connects a local power supply and/or a ground of one or more circuit blocks, hereinafter referred to as a gated domain, to a main or continuous power supply and/or ground, respectively. The gating switch has a low impedance in a closed (connecting) state, and a high impedance in an open (disconnecting) state. The power supply to the power gated domain can be enabled or disabled by changing the state of the gating switch. Thus, the power supply to a gated domain can be turned off temporarily when not needed, for example to reduce the overall power consumption of the integrated circuit or to reduce noise levels. This temporary shutdown is also referred to as “low power mode” or “inactive mode”. When the circuit blocks of the gated domain are required again, they are activated by “closing” the gating switch so as to transition the mode to an “active mode”, thereby electrically coupling the power supply or ground to the gated domain.
A number of different types of ESD stress is known. A first category are types related to a transfer of an electrostatic charge into the chip by a charged external body, such as a human body or machine, fixture, or tool, for example so-called “Human Body Model” (HBM) and so-called “Machine Model” (MM) ESD Another category relates to the chip, or an internal part thereof, itself being charged and the subsequent electrostatic discharge thereof, so-called “Charged Device Model” (CDM) ESD. In contrast to HBM and MM ESD stresses that originate from pins of a chip, via the CDM ESD stress is typically generated “internally” in the device, for example when a charged device in the gated domain discharges to a grounded surface through a device pin. Such a charge can build up by, for example, exposing an integrated circuit to an electromagnetic field.
Known circuits to protect gated domains from such CDM ESD stresses demonstrate acceptable performance provided that the power-up time of the gated domain is below a certain threshold. In this respect, CDM ESD stress protection circuits are known to trigger in response to a predetermined voltage level and/or a predetermined slew rate of the voltage level being monitored. The need to consider the slew rate of the power voltage has become increasingly important to be able to detect CDM ESD events in relation to modern circuit technologies, because voltage levels that are slightly higher than the voltage level of the power supply, for example by 10% to 15%, can result in device failure and so a more rapid detection than simply monitoring voltage levels is required. However, it has been discovered by the inventors that triggering of a CDM ESD protection circuit based at least partly upon slew rate as a parameter results in false triggering of the CDM ESD protection circuit when the power-up time of the gated domain conflicts with the slew rate to be detected by the CDM ESD protection circuit. To this end, falsely triggering the CDM ESD protection circuit results, for example, in the power supply terminal or node for the gated domain being short-circuited to ground potential, causing the power system of an integrated circuit to “collapse”, which is clearly disadvantageous. The alternative is not to provide gated domains of integrated circuits with CDM ESD stress protection, but this too is clearly disadvantageous.